Grain size engineering via a Hf0.5Zr0.5O2 seed layer for FeFET memory and synaptic devices

Abstract

This study demonstrates the use of a top-gate ferroelectric field effect transistor (FeFET) with the replacement electrode solid phase epitaxy (SPE) method and high deposition temperature during atomic layer deposition (ALD). By employing these engineering techniques, the average grain size was successfully reduced, and the formation of the non-ferroelectric monoclinic phase (m-phase) was effectively inhibited. In terms of ferroelectric properties, both the remanent polarization (2Pr) and coercive field (Ec) values demonstrated significant increases by 35% and 50%, respectively. Notably, improvements were observed in memory characteristics, with the memory window (MW) increasing from 0.3 V to 0.9 V and endurance enhancing by three orders of magnitude. In terms of synaptic properties, there was an enhancement in the number of conductance states from 100 to 136, an increase in the Gmax/Gmin ratio from 5.16 to 90, and an improvement in weight update linearity. The simulation results based on the MNIST dataset show an improvement in inference accuracy from 65% to 85%.