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A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees
- Issue Date
- May-2025
- Keywords
- current-mode logic (CML); feed-forward equalizers (FFE); four-level pulse-amplitude modulation (PAM-4); Transmitters
- Citation
- IEEE International Symposium on Circuits and Systems proceedings, pp 1 - 5
- Pages
- 5
- Indexed
- SCOPUS
- Journal Title
- IEEE International Symposium on Circuits and Systems proceedings
- Start Page
- 1
- End Page
- 5
- ISSN
- 0271-4302
2158-1525
- Abstract
- This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)