ARNorm: Hardware-Efficient Normalization for Lightweight Edge Models
- Authors
- Kim, Sunyeop; Rhee, Chae-eun
- Issue Date
- Sep-2025
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- AILayerNorm; Hardware Accelerator; INT8; Layer Normalization; Quantization; RMSNorm; Transformer; Vision Trans-former
- Citation
- 2025 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2025, pp 1 - 3
- Pages
- 3
- Indexed
- SCOPUS
- Journal Title
- 2025 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2025
- Start Page
- 1
- End Page
- 3
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/208916
- DOI
- 10.1109/ITC-CSCC66376.2025.11137703
- ISSN
- 2997-7401
2997-741X
- Abstract
- We propose ARNorm, a hardware-friendly normalization algorithm designed for efficient inference in transformer-based models. ARNorm combines the structural simplicity of RMSNorm [1] with the hardware-optimized techniques of AILayerNorm, introduced in SOLE [2] achieving accurate normalization using only 8-bit integer precision (INT8) arithmetic. By employing dynamic compression and a priority encoder-based Look-Up Table (LUT) for root approximation, ARNorm eliminates costly floating-point operations such as mean, variance, and square root calculations. Experiments on six pre-trained Vision Transformer models demonstrate that ARNorm reduces quantization error by up to 10% compared to AILayerNorm and maintains accuracy comparable to 32-bit floating point precision(FP32)-based RMSNorm, making it highly suitable for edge and embedded AI applications.
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