A 400-MS/s 2-b/cycle Second-order Noise-shaping SAR ADC Using FIA-based Ring Amplifier

Abstract

This paper presents a 2-bit/cycle second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a floating inverter amplifier (FIA)-based ring amplifier (FBRA) and offset-calibrated comparators. The proposed ADC employs a 2-bit/cycle structure for high-speed operation, utilizing a reference capacitive digital-to-analog converter (CDAC), a signal CDAC, and three comparators. To mitigate the degradation of the signal-to-noise-and-distortion ratio (SNDR) caused by the different offset voltages of multiple comparators, an offset calibration circuit is designed. A cascade of integrators with feedforward (CIFF) structure is designed using an active integrator with an FBRA. The proposed ADC is designed in a 28-nm process with 1-V power supply. The SPICE simulation results show that the ADC achieves an SNDR of 71 dB with a power consumption of 3.2 mW, when operated with a sampling rate of 400-MS/s and an oversampling ratio (OSR) of 8 resulting in a Schreier figure-of-merit (FoM) of 172 dB.