High-temperature interfacial stability of In2O3 FETs with SiO2 versus Al2O3 insulators enabling 3 nm channel scaling

Abstract

Dynamic random-access memory (DRAM) scaling demands channel materials that maintain electrical stability and retention under high-temperature processing. Oxide semiconductors, particularly indium oxide (In2O3), offer wide bandgaps, high electron mobility, and excellent uniformity, making them promising candidates for advanced DRAM architectures. In this study, we systematically investigate the interfacial and thermal stability of In2O3 channels with aluminum oxide (Al2O3) and silicon dioxide (SiO2) dielectrics under high-temperature conditions representative of DRAM backend processing. Capacitance–voltage measurements reveal a 26% increase in interface-trap density for In2O3/Al2O3 stacks after annealing at 700 °C, whereas In2O3/SiO2 stacks exhibit an 18% reduction, indicating the superior interfacial robustness of SiO2. In2O3 field-effect transistors (FETs) with a 5 nm channel thickness maintain high field-effect mobility (>80 cm2 V−1 s−1) after annealing at 700 °C, independent of the passivation layer material. At a 3 nm channel thickness, the Al2O3-passivated In2O3 FET shows severe mobility degradation, whereas the SiO2-passivated device maintains high mobility. SiO2 shows superior chemical and diffusion stability compared to Al2O3 after high-temperature annealing, highlighting the critical impact of interfacial diffusion and defect formation on ultrathin In2O3 channel performance. This study highlights the importance of dielectric selection, interfacial control, and channel-thickness optimization for reliable integration of oxide–semiconductor channels in next-generation DRAM devices.