Scaling Effects on Memory Characteristics of Ferroelectric Field-effect Transistors

Abstract

In this study, we investigated the geometric scaling effects on the memory characteristics of ferroelectric field-effect transistors (FeFETs) with nanosheet structures. It was observed that the memory window (MW) reduced as the gate stack got thinner, the active width became narrower, and the channel length increased. By analyzing the correlation between gate current, low-frequency noise, and MW/switching speeds, it was found that excessive gate stack thickness scaling degraded the MW by charge trapping. Moreover, it was revealed that the MW diminished with narrower width by polarization compensation at the active corner and with longer length by process damage-induced ferroelectricity enhancement at gate edges, respectively.