A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

Abstract

In this paper, a four-level pulse amplitude modulation (PAM-4) receiver for single-ended memory interfaces is presented. The frontend signaling path is optimized to maximize the receivers bandwidth in combination with a T-coil that mitigates the loading effect of the electrostatic discharge (ESD) protection cell. The following continuous-time linear equalizer (CTLE) employs an inverter-based TAS-transimpedance (TIA) stage in a subtraction configuration to compensate for the channel loss. The dual-path T-coil is optimally designed for the CTLE core based on the characteristics of the low and high-frequency signaling paths of the subtractive equalizer to maximize the bandwidth of the high-frequency path. The complementary transconductances with current biasing achieve high gain, wide linearity, and high power supply rejection ratio (PSRR). The output common-mode of the CTLE is balanced across the entire input range by adopting an auxiliary TAS and suppressing the gain mismatch. The proposed single-ended PAM-4 receiver is fabricated in a 40-nm CMOS technology and occupies 0.014 mm2. The design operates at 28-Gb/s with a 10-12 bit error rate (BER) and consumes 21.51 mW, which corresponds to 0.77-pJ/bit energy efficiency.