Engineering metal/oxide interfaces in IGZO thin-film transistors via atomic-layer-grown SiO2 interlayers for improved contact performance
- Authors
- Hwang, Taewon; Lim, So Young; Song, Jeong-Su; Lee, Sangwoo; Park, Jin-Seong
- Issue Date
- Feb-2026
- Publisher
- ELSEVIER
- Keywords
- IGZO; Atomic layer deposition; Ultrathin interlayer; Contact resistance; Fowler-Nordheim tunneling
- Citation
- APPLIED SURFACE SCIENCE, v.720, pp 1 - 8
- Pages
- 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- APPLIED SURFACE SCIENCE
- Volume
- 720
- Start Page
- 1
- End Page
- 8
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/212047
- DOI
- 10.1016/j.apsusc.2025.165143
- ISSN
- 0169-4332
1873-5584
- Abstract
- This study systematically investigated the impact of ultrathin SiO<inf>2</inf> interlayers on the contact performance of IGZO thin-film transistors. Atomic layer deposition was used to precisely deposit SiO<inf>2</inf> layers with thicknesses ranging from 0 to 1 nm at the IGZO channel and metal electrode interface. At an optimal interlayer thickness of 0.25 nm, the field-effect mobility increased from 19.92 to 24.10 cm2/V·s, whereas the contact resistance was reduced from 34.9 to 17.6 Ω·cm based on the transmission line method (TLM) analysis. Cross-bridge Kelvin resistor (CBKR) measurements further revealed a decrease in specific contact resistivity from 1.96 × 10−4 to 5.9 × 10−5 Ω·cm2, confirming a ∼70 % reduction. The consistent trends obtained from the TLM and CBKR analyses validated that the mobility improvement stemmed primarily from enhanced carrier injection at the metal–semiconductor interface. High-resolution transmission electron microscopy imaging revealed a uniform insulating interlayer at the Mo/IGZO interface, indicating precise interface engineering to be a key factor in performance enhancement. Fowler–Nordheim tunneling analysis further demonstrated that the carrier injection was dominated by tunneling mechanisms rather than thermionic emission. These results confirm that ultrathin insulating interlayers could effectively suppress Fermi-level pinning, maintaining sufficient tunneling probability, thus presenting a viable method of reducing the contact resistance and enhancing the oxide semiconductor device performance considerably.
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