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Low-power counter for column-parallel CMOS image sensors
- Authors
- Kim, Jong-Seok; Yoon, Jin-O; Choi, Byong-Deok
- Issue Date
- Jan-2017
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- CMOS image sensor (CIS); column-parallel ADC; correlated double sampling (CDS); counter
- Citation
- 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, pp.554 - 556
- Indexed
- SCOPUS
- Journal Title
- 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
- Start Page
- 554
- End Page
- 556
- ISSN
- 0000-0000
- Abstract
- A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.
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Related Researcher
- CHOI, BYONG DEOK
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)