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Bonding based channel transfer and low temperature process for monolithic 3D integration platform development
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, R. | - |
| dc.contributor.author | Yu, H.-Y. | - |
| dc.contributor.author | Kim, H. | - |
| dc.contributor.author | Ryu, H.-Y. | - |
| dc.contributor.author | Bae, H.-K. | - |
| dc.contributor.author | Choi, K.K. | - |
| dc.contributor.author | Cha, Y.-W. | - |
| dc.contributor.author | Choi, Chang hwan | - |
| dc.date.accessioned | 2021-08-02T15:52:15Z | - |
| dc.date.available | 2021-08-02T15:52:15Z | - |
| dc.date.created | 2021-05-11 | - |
| dc.date.issued | 2017-01 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/21259 | - |
| dc.description.abstract | We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Bonding based channel transfer and low temperature process for monolithic 3D integration platform development | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Choi, Chang hwan | - |
| dc.identifier.doi | 10.1109/S3S.2016.7804407 | - |
| dc.identifier.scopusid | 2-s2.0-85011317254 | - |
| dc.identifier.bibliographicCitation | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 | - |
| dc.relation.isPartOf | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 | - |
| dc.citation.title | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Conference Paper | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Bonding | - |
| dc.subject.keywordPlus | Chemical bonds | - |
| dc.subject.keywordPlus | Epitaxial growth | - |
| dc.subject.keywordPlus | Integration | - |
| dc.subject.keywordPlus | Ion implantation | - |
| dc.subject.keywordPlus | Logic gates | - |
| dc.subject.keywordPlus | Low temperature operations | - |
| dc.subject.keywordPlus | Microelectronics | - |
| dc.subject.keywordPlus | Monolithic integrated circuits | - |
| dc.subject.keywordPlus | Silicon wafers | - |
| dc.subject.keywordPlus | Three dimensional integrated circuits | - |
| dc.subject.keywordPlus | Wafer bonding | - |
| dc.subject.keywordPlus | 3-D integration | - |
| dc.subject.keywordPlus | Channel transfer | - |
| dc.subject.keywordPlus | Gate stacks | - |
| dc.subject.keywordPlus | Laser annealing | - |
| dc.subject.keywordPlus | Low power application | - |
| dc.subject.keywordPlus | Low temperature bonding | - |
| dc.subject.keywordPlus | Low temperatures | - |
| dc.subject.keywordPlus | Low- temperature process | - |
| dc.subject.keywordPlus | Temperature | - |
| dc.subject.keywordAuthor | Epitaxial Growth | - |
| dc.subject.keywordAuthor | Gate Stack | - |
| dc.subject.keywordAuthor | Laser Annealing | - |
| dc.subject.keywordAuthor | Low Temperature Bonding | - |
| dc.subject.keywordAuthor | Monolithic 3D | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/7804407 | - |
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Related Researcher
- Choi, Chang hwan
- COLLEGE OF ENGINEERING (SCHOOL OF MATERIALS SCIENCE AND ENGINEERING)