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Bonding based channel transfer and low temperature process for monolithic 3D integration platform development
- Authors
- Choi, R.; Yu, H.-Y.; Kim, H.; Ryu, H.-Y.; Bae, H.-K.; Choi, K.K.; Cha, Y.-W.; Choi, Chang hwan
- Issue Date
- Jan-2017
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Epitaxial Growth; Gate Stack; Laser Annealing; Low Temperature Bonding; Monolithic 3D
- Citation
- 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
- Indexed
- SCOPUS
- Journal Title
- 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
- ISSN
- 0000-0000
- Abstract
- We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
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Related Researcher
- Choi, Chang hwan
- COLLEGE OF ENGINEERING (SCHOOL OF MATERIALS SCIENCE AND ENGINEERING)