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100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm Technology

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dc.contributor.authorSong, Eunji-
dc.contributor.authorYang, Jeonghyu-
dc.contributor.authorOh, Youngmin-
dc.contributor.authorHong, Seungwook-
dc.contributor.authorLee, Dongjun-
dc.contributor.authorLee, Sangwan-
dc.contributor.authorIm, Hyunwoo-
dc.contributor.authorShin, Taeho-
dc.contributor.authorHan, Jaeduk-
dc.date.accessioned2026-05-11T03:00:09Z-
dc.date.available2026-05-11T03:00:09Z-
dc.date.issued2025-02-
dc.identifier.issn0018-9200-
dc.identifier.issn1558-173X-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/212639-
dc.description.abstractThis article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100-and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid 3+1 tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit.-
dc.format.extent12-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.title100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm Technology-
dc.title.alternative100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/JSSC.2024.3492061-
dc.identifier.scopusid2-s2.0-85209915984-
dc.identifier.wosid001358229600001-
dc.identifier.bibliographicCitationIEEE Journal of Solid-State Circuits, v.60, no.2, pp 543 - 554-
dc.citation.titleIEEE Journal of Solid-State Circuits-
dc.citation.volume60-
dc.citation.number2-
dc.citation.startPage543-
dc.citation.endPage554-
dc.type.docTypeArticle; Early Access-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlus56 GB/S NRZ-
dc.subject.keywordPlus3-TAP FFE-
dc.subject.keywordAuthorCascode-
dc.subject.keywordAuthorhigh-voltage drivers-
dc.subject.keywordAuthormultiplexers-
dc.subject.keywordAuthorpredrivers-
dc.subject.keywordAuthortransmitters-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/10752934-
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