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100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm Technology
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Song, Eunji | - |
| dc.contributor.author | Yang, Jeonghyu | - |
| dc.contributor.author | Oh, Youngmin | - |
| dc.contributor.author | Hong, Seungwook | - |
| dc.contributor.author | Lee, Dongjun | - |
| dc.contributor.author | Lee, Sangwan | - |
| dc.contributor.author | Im, Hyunwoo | - |
| dc.contributor.author | Shin, Taeho | - |
| dc.contributor.author | Han, Jaeduk | - |
| dc.date.accessioned | 2026-05-11T03:00:09Z | - |
| dc.date.available | 2026-05-11T03:00:09Z | - |
| dc.date.issued | 2025-02 | - |
| dc.identifier.issn | 0018-9200 | - |
| dc.identifier.issn | 1558-173X | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/212639 | - |
| dc.description.abstract | This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100-and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid 3+1 tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit. | - |
| dc.format.extent | 12 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | 100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm Technology | - |
| dc.title.alternative | 100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/JSSC.2024.3492061 | - |
| dc.identifier.scopusid | 2-s2.0-85209915984 | - |
| dc.identifier.wosid | 001358229600001 | - |
| dc.identifier.bibliographicCitation | IEEE Journal of Solid-State Circuits, v.60, no.2, pp 543 - 554 | - |
| dc.citation.title | IEEE Journal of Solid-State Circuits | - |
| dc.citation.volume | 60 | - |
| dc.citation.number | 2 | - |
| dc.citation.startPage | 543 | - |
| dc.citation.endPage | 554 | - |
| dc.type.docType | Article; Early Access | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | 56 GB/S NRZ | - |
| dc.subject.keywordPlus | 3-TAP FFE | - |
| dc.subject.keywordAuthor | Cascode | - |
| dc.subject.keywordAuthor | high-voltage drivers | - |
| dc.subject.keywordAuthor | multiplexers | - |
| dc.subject.keywordAuthor | predrivers | - |
| dc.subject.keywordAuthor | transmitters | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/10752934 | - |
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