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100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm Technology100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology

Other Titles
100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology
Authors
Song, EunjiYang, JeonghyuOh, YoungminHong, SeungwookLee, DongjunLee, SangwanIm, HyunwooShin, TaehoHan, Jaeduk
Issue Date
Feb-2025
Publisher
Institute of Electrical and Electronics Engineers
Keywords
Cascode; high-voltage drivers; multiplexers; predrivers; transmitters
Citation
IEEE Journal of Solid-State Circuits, v.60, no.2, pp 543 - 554
Pages
12
Indexed
SCIE
SCOPUS
Journal Title
IEEE Journal of Solid-State Circuits
Volume
60
Number
2
Start Page
543
End Page
554
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/212639
DOI
10.1109/JSSC.2024.3492061
ISSN
0018-9200
1558-173X
Abstract
This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100-and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid 3+1 tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit.
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