A 96-Gb/s 1.6-V ppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology

Abstract

This brief presents an eight-level pulse amplitude modulation (PAM-8) transmitter (TX) with three-tap feed-forward equalization (FFE), utilizing a cascaded current mode logic (CML) PAM-8 main driver and dual-path PAM-4/2 predrivers. The PAM-4/2 signals from predrivers are combined in the PAM-8 main driver to produce an eight-level signal with small output loading compared to conventional drivers, enabling high-speed data transmission. The main driver incorporates shunt transistors to realize the variable FFE function without disturbing its operating conditions for robust pulse amplitude modulation (PAM) signal combining. The prototype TX was fabricated using a 40-nm planar CMOS process, achieving 96-Gb/s data rate and 50-mV worst case vertical eye-opening while consuming 349.74 mW, corresponding to 3.64-pJ/bit energy efficiency.