Circuit design of physical unclonable function for security applications in standard CMOS technology
- Authors
- Jeon, Duhyun; Choi, Byong-Deok
- Issue Date
- Dec-2016
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- authentication; Physical unclonable function; process variation; secret key; via formation
- Citation
- 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, pp 86 - 90
- Pages
- 5
- Indexed
- SCOPUS
- Journal Title
- 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
- Start Page
- 86
- End Page
- 90
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/21323
- DOI
- 10.1109/EDSSC.2016.7785216
- Abstract
- The physical unclonable function (PUF) for generating unique bit strings has been tried using process variations in semiconductor fabrication. It can find various applications in hardware security area such as authentication or secure key storage. The unique secure information should not be changed over time in various environmental conditions such as temperature and supply voltage variations. This requirement is represented by the reliability of a PUF. Most of the previous PUFs are based on the mismatches between two circuit elements such as two transistors with an identical layout. However, in case the mismatches are very minute, the PUF response can be easily affected by changes in the external environments. Moreover, the characteristics can vary with the temperature variation. Some techniques including preselection method and use of error correction code (ECC) have been proposed to overcome this reliability issue, but they need non-volatile memories, and significantly increase the circuit area and the power consumption. On the other hand, the physical-based PUF only makes use of the probability that the conducting layers in a semiconductor chip are physically connected. Once the connection state is determined during a semiconductor process, it is not changed with the temperature or supply voltage variations. The VIA-PUF, one of the physical-based PUFs, can generate the random responses if the via hole size is properly chosen smaller than regulated by the design rule. The VIA-PUF is fabricated in a 0.18μm CMOS process and evaluated with 119 chips, each of which has 2,560 bits. The experiments show that the YIA-PUF shows no bit error throughout 1,000 times repeated measurement for 96 hours at 125 °C.
- Files in This Item
-
Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/21323)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.