Hydrogen-State-Engineered Oxide Semiconductor Channels Enabling Reliable 2T0C DRAM Operation

Abstract

Precise control of hydrogen incorporation is critical for optimizing oxide semiconductor devices. To this end, a three-step annealing strategy is presented to modulate hydrogen incorporation and its passivation behavior in atomic-layer-deposited In–Ga–O (IGO) transistors. Dry-air pre-annealing at 600°C induces crystallization and sets a baseline for hydrogen uptake, pressurized hydrogen annealing (1–30 bar) incorporates hydrogen for defect passivation, and final dry-air annealing at 600°C removes excess hydrogen while preserving favorable bonds. Depth-profiled dynamic secondary ion mass spectrometry and capacitance–voltage analysis showed reduced interface trap density and flat band voltage shift, with a minimum interface trap density of 9.57 × 1011 eV−1 cm−2 and flat band voltage shift of 0.027 V at 10 bar. Electrical measurements confirm high field-effect mobility over 70 cm2 V−1 s−1, a near ideal subthreshold swing of 72.8 mV dec−1, and negligible hysteresis, alongside the improved positive bias temperature stress stability of ΔVth = +0.06 V at 95°C. The optimized process implemented in IGO-based two transistor-zero capacitor dynamic random-access memory yields a retention time of 309.311 s at 85°C. This method provides a practical route to achieve a reliable oxide semiconductor memory compatible with hydrogen-rich back-end processing.