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Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN

Authors
Hyun, JinhoonJeong, InchulChu, ShinhoLim, Jaemyung
Issue Date
Apr-2026
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Random access memory; Metals; Iterative methods; Circuits; Voltage measurement; Integrated circuit modeling; Computer architecture; Estimation; Microprocessors; Computational modeling; DRAM power integrity; high-bandwidth memory (HBM); IR-drop; on-chip power delivery network (PDN)
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.45, no.4, pp 1782 - 1786
Pages
5
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume
45
Number
4
Start Page
1782
End Page
1786
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/213963
DOI
10.1109/TCAD.2025.3607129
ISSN
0278-0070
1937-4151
Abstract
In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.
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COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
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