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RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation
- Authors
- 김지훈
- Issue Date
- 29-Sep-2025
- Place
- Taipei International Convention Center (TICC)
- Conference Name
- CODES+ISSS 2025
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 2. Conference Papers
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Related Researcher
- Kim, Ji Hoon
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)