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Unveiling the Hybrid-Channel (poly-Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL-Assisted Erase Operation

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dc.contributor.authorChoi, Su-Hwan-
dc.contributor.authorSim, Jae-Min-
dc.contributor.authorShin, Jeongmin-
dc.contributor.authorRyu, Seong-Hwan-
dc.contributor.authorHwang, Taewon-
dc.contributor.authorLim, So Young-
dc.contributor.authorOh, Hye-Jin-
dc.contributor.authorKwag, Jae-Hyeok-
dc.contributor.authorLee, Jun-Yeoub-
dc.contributor.authorSong, Ki-Cheol-
dc.contributor.authorLee, Yeonhee-
dc.contributor.authorSong, Minju-
dc.contributor.authorKim, Junghwan-
dc.contributor.authorPark, Chang-Kyun-
dc.contributor.authorSong, Yun-Heub-
dc.contributor.authorPark, Jin-Seong-
dc.date.accessioned2026-07-15T07:30:15Z-
dc.date.available2026-07-15T07:30:15Z-
dc.date.issued2025-05-
dc.identifier.issn2688-4062-
dc.identifier.issn2688-4062-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/219185-
dc.description.abstractOxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field-effect mobility and superior large-area uniformity but suffering from low thermal stability, trade-off between mobility and stability, and the impossibility of the erase operation. To address these drawbacks, herein a hybrid-channel structure comprising heterostacked poly-Si and In–Ga–O (IGO) is developed. IGO is used as the main channel to achieve thermal stability above 800 °C, and the fabrication process is optimized to achieve superior electrical properties (μFE = 103.66 cm2 V−1 s−1, subtreshold swing = 96 mV decade−1) and reliability (0.07 V positive shift during the positive bias temperature stress of 3 MV cm−1 at 100 °C for almost 3 h). Poly-Si is used to generate the gate-induced drain leakage current and enable the erase operation. The developed structure is used to fabricate 2D planar and three-layer stacked 3D NAND flash memories. The superior electrical properties (μFE = 116.08 cm2 V−1 s−1, Ion = 4.73 μA μm−1) and deviations of the hybrid-channel NAND memory are comparable with those of its OS-channel counterpart. The use of the hybrid-channel structure in the NAND memories enables the realization of the erase operation with a large memory window (≈3.60 V).-
dc.format.extent10-
dc.language영어-
dc.language.isoENG-
dc.publisherWILEY-V C H VERLAG GMBH-
dc.titleUnveiling the Hybrid-Channel (poly-Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL-Assisted Erase Operation-
dc.typeArticle-
dc.publisher.location독일-
dc.identifier.doi10.1002/sstr.202400495-
dc.identifier.scopusid2-s2.0-85212924345-
dc.identifier.wosid001382768900001-
dc.identifier.bibliographicCitationSMALL STRUCTURES, v.6, no.5, pp 1 - 10-
dc.citation.titleSMALL STRUCTURES-
dc.citation.volume6-
dc.citation.number5-
dc.citation.startPage1-
dc.citation.endPage10-
dc.type.docTypeArticle in press-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaChemistry-
dc.relation.journalResearchAreaScience & Technology - Other Topics-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalWebOfScienceCategoryChemistry, Physical-
dc.relation.journalWebOfScienceCategoryNanoscience & Nanotechnology-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.subject.keywordPlusTHIN-FILM TRANSISTORS-
dc.subject.keywordPlusSI FILMS-
dc.subject.keywordPlusOXIDE-
dc.subject.keywordPlusMOBILITY-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusTHRESHOLD-
dc.subject.keywordPlusELECTRON-
dc.subject.keywordAuthor3D NAND flash memories-
dc.subject.keywordAuthoratomic layer deposition-
dc.subject.keywordAuthorcrystallinity-
dc.subject.keywordAuthorgate-induced drain leakage erase operation-
dc.subject.keywordAuthorhybrid channel (poly-Si/In–Ga–O)-
dc.identifier.urlhttps://onlinelibrary.wiley.com/doi/10.1002/sstr.202400495-
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서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
서울 공과대학 > 서울 신소재공학부 > 1. Journal Articles

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