High performance DRAM architecture with split row buffer
- Authors
- Lee, Min Kyu; Chung, Ki Seok
- Issue Date
- Oct-2016
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- DRAM chips; memory architecture; buffer storage; performance evaluation; multiprocessing systems; memory-intensive applications; system performance; precharge operations; activate operations; write commands; read commands; latency penalty; heterogeneous multicore system; access latency improvement; performance metrics; dynamic random access memory; split row buffer; high performance DRAM architecture
- Citation
- ELECTRONICS LETTERS, v.52, no.22, pp.1844 - 1845
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 52
- Number
- 22
- Start Page
- 1844
- End Page
- 1845
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/22158
- DOI
- 10.1049/el.2016.1111
- ISSN
- 0013-5194
- Abstract
- In dynamic random access memory (DRAM)-based main memory, access latency is a key performance metric. Commonly, the access latency is improved by employing row buffers that store the most recently accessed row data. However, if a new request tries to access a different row address from that in the row buffer, which is a row buffer conflict, the access latency is significantly increased. In a heterogeneous multi-core system, row buffer conflicts occur frequently because various types of processors with different access patterns share the main memory. A novel DRAM architecture that hides the latency penalty due to row buffer conflicts is proposed. The key idea is that read or write commands serviced during activate and precharge operations for different rows in the same bank are carried out by splitting the row buffer into two buffers. Experimental results show that the proposed DRAM architecture achieves up to 16% higher system performance for memory-intensive applications compared with a conventional DRAM architecture.
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