Skew cancellation technique for > 256-Gbyte/s high-bandwidth memory (HBM)
- Authors
- Ahn, Key-One; Yoon, Chong Seung
- Issue Date
- Jun-2016
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.52, no.13, pp.1155 - 1156
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 52
- Number
- 13
- Start Page
- 1155
- End Page
- 1156
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/23030
- DOI
- 10.1049/el.2015.4001
- ISSN
- 0013-5194
- Abstract
- The skews among multi-Gbit/s data signals of through-silicon-via-based parallel DRAM interface are cancelled without any overhead on DRAM dies. All the skew cancelling circuits are realised on a logic die which cancels the write and read path skews separately. A prototype chip with the proposed skew cancellation has been implemented in a 65 nm standard CMOS technology. After the skew cancellation, the residual skew of read and write paths are 12 and 18 ps, respectively.
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