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A novel bit flipping decoder for systematic LDPC codesopen access
- Authors
- Lim, Jinsoo; Shin, Dong-Joon
- Issue Date
- Jun-2017
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- bit flipping; CRC; low-power LDPC decoder; normalized minsum algorithm
- Citation
- IEICE ELECTRONICS EXPRESS, v.14, no.2, pp.1 - 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 14
- Number
- 2
- Start Page
- 1
- End Page
- 8
- ISSN
- 1349-2543
- Abstract
- In this letter, a novel bit flipping decoding of systematic LDPC codes is proposed. Unsuccessfully decoded codeword is efficiently redecoded by the candidate information bit flipping (CIBF) decoder using cyclic redundancy check (CRC) information at the end of each iteration. We adopt the CIBF decoder to the LDPC decoding additionally and that makes it possible to reduce the power consumption up to 12.7% because of the reduced average number of iterations and to improve the frame error rate (FER) performance. Based on the hardware cost analysis in the CMOS cell library, the additional hardware cost of the CIBF decoder is negligible compared with the conventional LDPC decoder.
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Related Researcher
- Shin, Dong-Joon
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)