False history filtering for reducing hardware overhead of FPGA-based LZ77 compressor
- Authors
- Choi, Seungdo; Kim, Youngil; Song, Yong Ho
- Issue Date
- Aug-2018
- Publisher
- ELSEVIER
- Keywords
- Data compression; Data preprocessing; Programmable logic devices
- Citation
- JOURNAL OF SYSTEMS ARCHITECTURE, v.88, pp.110 - 119
- Indexed
- SCIE
SCOPUS
- Journal Title
- JOURNAL OF SYSTEMS ARCHITECTURE
- Volume
- 88
- Start Page
- 110
- End Page
- 119
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/2693
- DOI
- 10.1016/j.sysarc.2018.06.001
- ISSN
- 1383-7621
- Abstract
- Compression reduces the size of data by replacing original data with shorter bits of code or eliminating unnecessary data, thereby reducing the cost of storing and transmitting data. To reduce CPU load caused by compression, there are many cases where compression is accelerated through parallelization on additional hardware. The higher degree of parallelism leads to a higher processing bandwidth of hardware. However, it also causes a significant increase in hardware resource cost. In this paper, we propose a false history filtering technique that is used by a parallel hardware accelerator to avoid excessive hardware resource cost. This technique detects unnecessary string comparison operations that generate meaningless or unused results. The parallel hardware accelerator with false history filtering has no performance degradation even if the hardware uses less parallelized modules. Experimental results showed that the hardware LZ77 compressor with false history filtering reduces hardware usage by 5.18-18.35% without performance degradation.
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