A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Abstract

This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is +/- 15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm(2).