Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns
DC Field | Value | Language |
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dc.contributor.author | Kim, Sang-Kon | - |
dc.date.available | 2021-03-17T06:49:04Z | - |
dc.date.created | 2021-02-26 | - |
dc.date.issued | 2020-11 | - |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/11493 | - |
dc.description.abstract | The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | - |
dc.title | Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sang-Kon | - |
dc.identifier.doi | 10.1166/jnn.2020.18814 | - |
dc.identifier.wosid | 000554982500056 | - |
dc.identifier.bibliographicCitation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.20, no.11, pp.6912 - 6915 | - |
dc.relation.isPartOf | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.citation.title | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.citation.volume | 20 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 6912 | - |
dc.citation.endPage | 6915 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordAuthor | Lithography | - |
dc.subject.keywordAuthor | Lithography Simulation | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | EUV | - |
dc.subject.keywordAuthor | Line Edge Roughness | - |
dc.subject.keywordAuthor | LER | - |
dc.subject.keywordAuthor | TCAD | - |
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