Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns

Abstract

The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations.