A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication
- Authors
- Park, Dongjun; Kim, Jongsun
- Issue Date
- Oct-2020
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- MDLL; multiplying delay-locked loop; jitter; frequency multiplication; clock generation
- Citation
- IEICE ELECTRONICS EXPRESS, v.17, no.19
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 17
- Number
- 19
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/11506
- DOI
- 10.1587/elex.17.20200296
- ISSN
- 1349-2543
- Abstract
- A new all-digital multiplying delay-locked loop (MDLL) based frequency multiplier architecture with a high frequency multiplication factor N of 256 is presented. The proposed MDLL utilizes a dithering jitter reduction scheme based on a delta-sigma modulation to achieve a low deterministic jitter and a large N factor. Additionally, a new stochastic phase detector is proposed to reduce static phase offset and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed all-digital MDLL generates 2.4-GHz output clock and achieves a peak-topeak jitter of 6.47 ps with N = 256. It occupies an active area of 0.032 mm(2) and achieves a power efficiency of 0.875 mW/GHz.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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