A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL
DC Field | Value | Language |
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dc.contributor.author | Park, Dongjun | - |
dc.contributor.author | Kim, Jongsun | - |
dc.date.available | 2021-03-17T06:54:31Z | - |
dc.date.created | 2021-02-26 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 0278-081X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/11772 | - |
dc.description.abstract | This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65-7.0 GHz and occupies an area of only 0.021 mm(2). The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p-p) jitter of the output clock is about 4.55 ps at 7 GHz. | - |
dc.publisher | SPRINGER BIRKHAUSER | - |
dc.title | A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Jongsun | - |
dc.identifier.doi | 10.1007/s00034-019-01230-x | - |
dc.identifier.scopusid | 2-s2.0-85070759892 | - |
dc.identifier.wosid | 000519159700001 | - |
dc.identifier.bibliographicCitation | CIRCUITS SYSTEMS AND SIGNAL PROCESSING, v.39, no.4, pp.1715 - 1734 | - |
dc.relation.isPartOf | CIRCUITS SYSTEMS AND SIGNAL PROCESSING | - |
dc.citation.title | CIRCUITS SYSTEMS AND SIGNAL PROCESSING | - |
dc.citation.volume | 39 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 1715 | - |
dc.citation.endPage | 1734 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DDR4 SDRAM | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordPlus | MM(2) | - |
dc.subject.keywordAuthor | DDR4 | - |
dc.subject.keywordAuthor | DDR5 | - |
dc.subject.keywordAuthor | SDRAM | - |
dc.subject.keywordAuthor | Delay-locked loop | - |
dc.subject.keywordAuthor | DLL | - |
dc.subject.keywordAuthor | Memory | - |
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