A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL
- Authors
- Park, Dongjun; Kim, Jongsun
- Issue Date
- Apr-2020
- Publisher
- SPRINGER BIRKHAUSER
- Keywords
- DDR4; DDR5; SDRAM; Delay-locked loop; DLL; Memory
- Citation
- CIRCUITS SYSTEMS AND SIGNAL PROCESSING, v.39, no.4, pp.1715 - 1734
- Journal Title
- CIRCUITS SYSTEMS AND SIGNAL PROCESSING
- Volume
- 39
- Number
- 4
- Start Page
- 1715
- End Page
- 1734
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/11772
- DOI
- 10.1007/s00034-019-01230-x
- ISSN
- 0278-081X
- Abstract
- This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65-7.0 GHz and occupies an area of only 0.021 mm(2). The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p-p) jitter of the output clock is about 4.55 ps at 7 GHz.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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