Design and implementation of ternary carry lookahead adder on FPGA

Abstract

Ternary value logic (TVL) has advantages over binary system, such as providing smaller chip area and faster computation speed. However, ternary hardware implementation is in theoretical, simulation levels. Moreover, no hardware description language for ternary logic is developed. In this paper, by representing 1 trit (trinary digit) with 2 bit, ternary logic is implemented and analyzed in FPGA. To specify the performance of TVL, ternary carry lookahead adder is implemented on FPGA and the speed and power dissipation of the arithmetic unit are measured. The performance of 21-trit ternary CLA is compared with 32-bit binary CLA. The results show that ternary CLA is faster up to 10.36% and consumes 13.54% less power than binary CLA. In addition, performances of ripple carry adder using both ternary and binary logic are simulated. © 2021 IEEE.