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Electrochemical Process for 3D TSV without CMP and Lithographic Processes

Authors
Koo, Ja-KyungLee, Jae-Ho
Issue Date
Mar-2014
Publisher
KOREAN INST METALS MATERIALS
Keywords
TSV; copper via filling; electropolishing; electroless plating; Cu/Sn bump
Citation
ELECTRONIC MATERIALS LETTERS, v.10, no.2, pp.485 - 490
Journal Title
ELECTRONIC MATERIALS LETTERS
Volume
10
Number
2
Start Page
485
End Page
490
URI
https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/16742
DOI
10.1007/s13391-014-8007-5
ISSN
1738-8090
Abstract
A serial electrochemical processes consisting of copper via filling, electropolishing, electroless copper plating and electroless tin plating were investigated for the 3D through silicon via (TSV) SiP application. Defect-free copper via filling was achieved by controlling current modes and additives. After via filling, electropolishing was performed to planarize over-plated copper. Electropolishing within the potential of mass-transfer region and with the assistance of additives, fine polished surface without thickness disparity was achieved. For bump formation process, electroless copper and tin plating which is a self-aligned process was applied. Consequently, Cu/Sn bump on via patterned wafer was obtain without using the conventional CMP and lithographic processes.
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