A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm
- Authors
- Han, Sangwoo; Kim, Jongsun
- Issue Date
- Apr-2013
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Duty-cycle corrector (DCC); successive approximation register (SAR); clock duty; clock tree; duty cycle
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.13, no.2, pp.152 - 156
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 13
- Number
- 2
- Start Page
- 152
- End Page
- 156
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/17160
- DOI
- 10.5573/JSTS.2013.13.2.152
- ISSN
- 1598-1657
- Abstract
- This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than +/- 0.86 % for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-mu m, 1.8-V CMOS process and occupies an active area of 0.075 mm(2).
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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