Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package
- Authors
- Jee, Y. K.; Yu, J.; Park, K. W.; Oh, T. S.
- Issue Date
- May-2009
- Publisher
- SPRINGER
- Keywords
- Chip-stack package; system-in-package; through-silicon via; Zn via; Sn-Zn via
- Citation
- JOURNAL OF ELECTRONIC MATERIALS, v.38, no.5, pp.685 - 690
- Journal Title
- JOURNAL OF ELECTRONIC MATERIALS
- Volume
- 38
- Number
- 5
- Start Page
- 685
- End Page
- 690
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/21865
- DOI
- 10.1007/s11664-008-0646-6
- ISSN
- 0361-5235
- Abstract
- Microvias of 50 mu m diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias.
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Collections - College of Engineering > Materials Science and Engineering Major > 1. Journal Articles
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