An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider
- Authors
- Kim, Jongsun
- Issue Date
- 2-Jan-2022
- Publisher
- MDPI
- Keywords
- clock generator; multiplying delay-locked loop; MDLL; frequency divider; SoC
- Citation
- ELECTRONICS, v.11, no.2
- Journal Title
- ELECTRONICS
- Volume
- 11
- Number
- 2
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/25117
- DOI
- 10.3390/electronics11020261
- ISSN
- 2079-9292
- Abstract
- A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-mu m 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm(2) and consumes a power of 10.3 mW at 1.0 GHz.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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