Low Power Gate Diffusion Input Full Adder using Floating Body

Abstract

Conventionally, a large number of transistors are required to make a 1-bit full adder. However, this affects the circuit's power consumption and delay and increases the overall area, which is a critical problem for modern high-level integration technology. Therefore, a 1-bit full adder based on Gate Diffusion Input (GDI) cell was proposed as an alternative method. It has less power consumption, faster speed, and a smaller area. In this paper, we propose a 1-bit full adder using floating body at the GDI cell. Simulations show that the proposed circuit decreases the average power consumption maintaining high performance and stability. It can also provide robust operation because of its high reliability on VDD and temperature variation. © 2021 IEEE.