An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication
- Authors
- Kim, Taeyeon; Choi, Sunguk; Han, S.; Kim, Jongsun
- Issue Date
- 2020
- Publisher
- IEEE
- Keywords
- Frequency Synthesizer; MDLL; Clock Generator
- Citation
- 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), pp.230 - 231
- Journal Title
- 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020)
- Start Page
- 230
- End Page
- 231
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/27996
- DOI
- 10.1109/ISOCC50952.2020.9332935
- ISSN
- 2163-9612
- Abstract
- A multiplying delay-locked loop (MDLL)-based alldigital frequency synthesizer for de-skewed N/M-ratio clock frequency synthesis is presented. By eliminating the analog components such as a charge pump, the proposed all-digital frequency synthesizer achieves low sensitivity to device mismatch, resulting in improved jitter characteristics. Fabricated in a 0.13gm 1.2-V CMOS process, the proposed all-digital MDLL achieves programmable N/M-ratio frequency multiplication, where N = 1-31 and M = 1 similar to 15. The proposed MDLL achieves a measured peak-to-peak jitter of about 12 ps at 1 GHz with N/M = 8/1. It occupies an active area of 0.035 mm(2), and dissipates 10.3 mW at 1.0 GHz.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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