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Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding

Authors
Lee, SeokhoKim, Youngmin
Issue Date
2020
Publisher
IEEE
Keywords
Hardware Accelerators; Quantization; Bit-Level Composability; Bit Fusion; Booth Fusion
Citation
2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), pp.73 - 74
Journal Title
2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020)
Start Page
73
End Page
74
URI
https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/27999
DOI
10.1109/ISOCC50952.2020.9332943
ISSN
2163-9612
Abstract
Recently, several attempts have been made to optimize Deep Neural Networks (DNNs) through various hardware acceleration methods. Among them, Bit Fusion, the dynamic bit-level fusion/decomposition hardware architecture, was noted. We introduce a new model structure, Booth Fusion, which makes dynamic bit-level operations more efficient by implementing Bit Fusion with booth encoding. Our design shows improvements in 16.4% for the number of LUT and 14.2% for throughput.
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