A MDLL-based Multi-Phase Clock Multiplier
- Authors
- Yoon, Junsub; Kim, Jongsun
- Issue Date
- 2016
- Publisher
- IEEE
- Keywords
- clock multiplier; clock generator; MDLL
- Citation
- 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.247 - 248
- Journal Title
- 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)
- Start Page
- 247
- End Page
- 248
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/28217
- ISSN
- 2163-9612
- Abstract
- A multiplying delay-locked loop (MDLL)-hased multiphase clock multiplier is presented. The proposed clock multiplier provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable fractional multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. The proposed clock multiplier is implemented in a 65 nm CMOS process and occupies an active area of 0.01 mm(2). It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.
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- Appears in
Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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