Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic Estimation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, M. | - |
dc.contributor.author | Lee, D. | - |
dc.contributor.author | Lee, S. | - |
dc.contributor.author | Kim, Y. | - |
dc.contributor.author | Lee, H.-M. | - |
dc.date.accessioned | 2023-02-28T01:43:08Z | - |
dc.date.available | 2023-02-28T01:43:08Z | - |
dc.date.created | 2023-02-28 | - |
dc.date.issued | 2022-01-01 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/30878 | - |
dc.description.abstract | Field-programmable gate arrays (FPGAs) are considered to be a suitable platform for various electronics thanks to high performance and reconfigurable structure, but security concerns for FPGAs should be addressed. Non-invasive attacks on FPGAs may extract configuration files, i.e. bitstream, which is stored in external non-volatile memory, to estimate data or modify it to inject malicious codes. To identify the weakness and provide solutions, researches on FPGA reverse engineering have been conducted. This paper proposes an automated tool for FPGA reverse engineering, targeting Xilinx FPGAs. The tool can extract bitstream from the external memory, identify the device type, and reconstruct the logic programmed in the FPGA based on bitstream analysis. © 2022 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic Estimation | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Y. | - |
dc.identifier.doi | 10.1109/ISOCC56007.2022.10031326 | - |
dc.identifier.scopusid | 2-s2.0-85148412925 | - |
dc.identifier.wosid | 000971297000157 | - |
dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2022, ISOCC 2022, pp.328 - 329 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
dc.citation.title | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
dc.citation.startPage | 328 | - |
dc.citation.endPage | 329 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | non-invasive attack | - |
dc.subject.keywordAuthor | reverse engineering | - |
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