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Data extraction from flash memory and reverse engineering using Xilinx 7 series FPGA boards
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, D. | - |
| dc.contributor.author | Lee, S. | - |
| dc.contributor.author | Cho, M. | - |
| dc.contributor.author | Lee, H.-M. | - |
| dc.contributor.author | Kim, Y. | - |
| dc.date.accessioned | 2023-02-28T01:43:11Z | - |
| dc.date.available | 2023-02-28T01:43:11Z | - |
| dc.date.created | 2023-02-28 | - |
| dc.date.issued | 2022-01-01 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/30880 | - |
| dc.description.abstract | In this paper, we introduce a general methodology of reverse engineering for Xilinx FPGA devices using flash memory for programming. Based on the structural analysis of the flash memory used for the most recent 7-Series FPGA, data extraction for reverse engineering is carried out targeting the flash memory with the help of a logic analyzer. The accuracy of the extracted bitstream is finally verified using the in-house reverse engineering tool. © 2022 IEEE. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Data extraction from flash memory and reverse engineering using Xilinx 7 series FPGA boards | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Y. | - |
| dc.identifier.doi | 10.1109/ISOCC56007.2022.10031296 | - |
| dc.identifier.scopusid | 2-s2.0-85148444108 | - |
| dc.identifier.wosid | 000971297000158 | - |
| dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2022, ISOCC 2022, pp.330 - 331 | - |
| dc.relation.isPartOf | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
| dc.citation.title | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
| dc.citation.startPage | 330 | - |
| dc.citation.endPage | 331 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordAuthor | bitstream | - |
| dc.subject.keywordAuthor | flash memory | - |
| dc.subject.keywordAuthor | FPGA | - |
| dc.subject.keywordAuthor | logic analyzer | - |
| dc.subject.keywordAuthor | Reverse Engineering | - |
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Related Researcher
- Kim, Young min
- Engineering (Electronic & Electrical Engineering)