An Energy Efficient 7.59-ENOB 50 MS/s Flash-SAR ADC in 65-nm CMOS

Abstract

This paper presents an energy-efficient flash-SAR ADC with a 7.59-ENOB and 50 MS/s sampling rate to address the conversion speed limitations of SAR ADCs and the area and power consumption limitations of flash ADCs. The proposed design reduces the cycle count needed for conversion compared to conventional SAR ADCs. The use of a rail-to-rail sensing comparator enables accurate output even at low voltage levels, and peripheral circuits such as C-DAC switching circuits are kept to a minimum to reduce area and power consumption. The proposed design is implemented using a 65-nm CMOS process and achieved 47.5 dB SNDR, 61.3 dB SFDR, and 46.3 fJ/conversion-step at an input frequency of 100 KHz and a sampling frequency of 50 MS/s. © 2023 IEEE.