계면 스위칭 멤리스터 소자 구조와 신경망 회로 성능에 대한 시뮬레이션 연구

Abstract

In this study, the architecture of an interfacial switching memristor, which has a metal-insulatormetalstructure of Pt/SrTiO3/Nb-SrTiO3 was investigated. The performance of a neural network that usesmemristors as its synapse components was also examined with system-level simulations. A finite elementsolver, COMSOL Multiphysics, was used to simulate synaptic device characteristics, specifically, theconductance change, using a series of pulses for a given architecture. An open-source software, NeuroSim, wasused to simulate the ability of the neural network to recognize and identify handwritten digits. Electrostatics,mass transport, and thermionic emission equations were numerically solved in a fully coupled manner tomodel the Schottky barrier height modulation at the Pt/SrTiO3 contact using the applied bias. The barrierheight is a function of the oxygen vacancy concentration in the SrTiO3 near the contact. The gradual changeof the oxygen vacancy concentration profile caused by successive pulses results in the gradual change ofconductance. Utilizing the simulations, the influences of device structure modification, and more specifically,changing the size of the Schottky contact, on long-term potentiation and depression were analyzed for planardevices. The results show that a smaller Schottky contact yields a higher digit recognition rate. Based on thisfinding, a three-dimensional device architecture that is vertically stackable was designed.