Neuromorphic Computing Using Random Synaptic Feedback Weights for Error Backpropagation in NAND Flash Memory-Based Synaptic Devices
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, S.-T. | - |
dc.contributor.author | Lee, J.-H. | - |
dc.date.accessioned | 2024-04-16T02:31:40Z | - |
dc.date.available | 2024-04-16T02:31:40Z | - |
dc.date.issued | 2023-03-01 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.issn | 1557-9646 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/32938 | - |
dc.description.abstract | This work proposes utilizing separate synaptic string array for error backpropagation in NAND flash memory-based synaptic architecture with random synaptic feedback weight. To enable error backpropagation, forward and backward propagations are processed in separate synaptic devices in forward and backward synaptic arrays, respectively. In addition, synaptic weights in forward synaptic array are updated at each iteration, while those in backward synaptic array are fixed to reduce burden of peripheral circuits and power consumption. The optimal conductance response is investigated considering the linearity of the conductance response and the ratio of maximum and minimum currents. Reliability characteristics are verified by retention, endurance, and pass bias disturbance measurement results. Hardware-based neural networks with random synaptic weight achieve an inference accuracy of 95.41%, which is comparable to that of 95.58% obtained with transposed weight. Hardware-based neural network simulations demonstrate that the inference accuracy of the proposed on-chip learning scheme hardly decreases compared to that of the off-chip learning even with increasing device variation. © 1963-2012 IEEE. | - |
dc.format.extent | 6 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Neuromorphic Computing Using Random Synaptic Feedback Weights for Error Backpropagation in NAND Flash Memory-Based Synaptic Devices | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/TED.2023.3237670 | - |
dc.identifier.scopusid | 2-s2.0-85147299165 | - |
dc.identifier.wosid | 000967364800027 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Electron Devices, v.70, no.3, pp 1019 - 1024 | - |
dc.citation.title | IEEE Transactions on Electron Devices | - |
dc.citation.volume | 70 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 1019 | - |
dc.citation.endPage | 1024 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Hardware neural networks | - |
dc.subject.keywordAuthor | in-memory computing | - |
dc.subject.keywordAuthor | NAND flash memory | - |
dc.subject.keywordAuthor | neuromorphic | - |
dc.subject.keywordAuthor | on-chip learning | - |
dc.subject.keywordAuthor | synaptic device | - |
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