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Neuromorphic Computing Using Random Synaptic Feedback Weights for Error Backpropagation in NAND Flash Memory-Based Synaptic Devices

Authors
Lee, S.-T.Lee, J.-H.
Issue Date
1-Mar-2023
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
Hardware neural networks; in-memory computing; NAND flash memory; neuromorphic; on-chip learning; synaptic device
Citation
IEEE Transactions on Electron Devices, v.70, no.3, pp 1019 - 1024
Pages
6
Journal Title
IEEE Transactions on Electron Devices
Volume
70
Number
3
Start Page
1019
End Page
1024
URI
https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/32938
DOI
10.1109/TED.2023.3237670
ISSN
0018-9383
1557-9646
Abstract
This work proposes utilizing separate synaptic string array for error backpropagation in NAND flash memory-based synaptic architecture with random synaptic feedback weight. To enable error backpropagation, forward and backward propagations are processed in separate synaptic devices in forward and backward synaptic arrays, respectively. In addition, synaptic weights in forward synaptic array are updated at each iteration, while those in backward synaptic array are fixed to reduce burden of peripheral circuits and power consumption. The optimal conductance response is investigated considering the linearity of the conductance response and the ratio of maximum and minimum currents. Reliability characteristics are verified by retention, endurance, and pass bias disturbance measurement results. Hardware-based neural networks with random synaptic weight achieve an inference accuracy of 95.41%, which is comparable to that of 95.58% obtained with transposed weight. Hardware-based neural network simulations demonstrate that the inference accuracy of the proposed on-chip learning scheme hardly decreases compared to that of the off-chip learning even with increasing device variation. © 1963-2012 IEEE.
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