An anti-harmonic MDLL for phase-aligned on-chip clock multiplication

Abstract

This paper presents a new anti-harmonic fractional-ratio multiplying delay-locked loop (FMDLL) based clock frequency multiplier for phase aligned on-chip clock generation. With the adoption of a new harmonic lock detector (HLD), the proposed FMDLL solves the harmonic lock problem in conventional MDLLs. The proposed FMDLL is capable of multiplying the input clock with fractional ratio (= N/M), unlike the traditional MDLL which can only multiply with integer ratio (= N). With the new FMDLL, it is possible to quickly change the output frequency or the multiplication factors during operation without a reset. Fabricated in a 65-nm CMOS process, the harmonic-free FMDLL occupies an active area of 0.013 mm(2), operates from 2 GHz to 4 GHz with programmable ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. At 4 GHz with N/M = 10/1, the measured p-p output clock jitter and RMS jitter are 25.6 ps and 2.62 ps, respectively. The proposed FMDLL consumes 7.16 mW at 4 GHz.