A 2-4GHz fast-locking frequency multiplying delay-locked loop
- Authors
- Kim, Jongsun; Bae, B-H
- Issue Date
- 25-Jan-2017
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- multiplying DLL; MDLL; frequency multiplier; clock generator; clock multiplier; fast locking; PLL; DLL
- Citation
- IEICE ELECTRONICS EXPRESS, v.14, no.2
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 14
- Number
- 2
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/6171
- DOI
- 10.1587/elex.13.20161056
- ISSN
- 1349-2543
- Abstract
- A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015mm2. It operates over a frequency range of 2.0-4.0 GHz with a programmable frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while consuming 6.7mW at 2 GHz from a 1.2V supply. Compared with the conventional architecture, the locking time has been reduced about 80%.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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