A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range
- Authors
- Son, Jisu; Jang, Young-Chan
- Issue Date
- 25-Nov-2019
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- successive approximation register; analog-to-digital converter; capacitor digital-to-analog converter
- Citation
- IEICE ELECTRONICS EXPRESS, v.16, no.22
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 16
- Number
- 22
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/128
- DOI
- 10.1587/elex.16.20190597
- ISSN
- 1349-2543
- Abstract
- A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a single-ended successive approximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8V. Its active area and power consumption are 0.207 mm(2) and 2.29 mW, respectively. The measured DNL and INL are +0.93/-0.51 LSBs and +0.61/-0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.
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