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A 3 Gbps/Lane MIPI D-PHY Transmission Buffer Chip
- Authors
- Lee, Pil-Ho; Jang, Young-Chan
- Issue Date
- Jun-2019
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- transmission buffer chip; LVDS; SLVS; MIPI D-PHY; FPGA-based frame generator
- Citation
- IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E102A, no.6, pp.783 - 787
- Volume
- E102A
- Number
- 6
- Start Page
- 783
- End Page
- 787
- ISSN
- 0916-8508
- Abstract
- A 3 Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
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Related Researcher
- JANG, YOUNG CHAN
- College of Engineering (School of Electronic Engineering)