A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme
- Authors
- Jang, Young-Chan
- Issue Date
- 10-Feb-2010
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- phase corrector; transmitter; QDR I/O; duty cycle detector
- Citation
- IEICE ELECTRONICS EXPRESS, v.7, no.3, pp.146 - 152
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 7
- Number
- 3
- Start Page
- 146
- End Page
- 152
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2784
- DOI
- 10.1587/elex.7.146
- ISSN
- 1349-2543
- Abstract
- A digital phase corrector is proposed to reduce the time jitter noise in a high speed parallel chip-to-chip interface system with a quad data rate (QDR) input/output (I/O) scheme. The proposed digital phase corrector for the 4-phase clock utilizes only one duty cycle detector by using a digitally controlled phase correction method and multiplexing function of transmitter for a QDR I/O scheme. Also, it reduces the static phase error generated in the transmitter, because of the inclusion of a replica of the transmitter in the feedback loop. To verify the proposed digital phase correction scheme, a digital phase corrector for the QDR I/O scheme with a 1.25GHz 4-phase clock was designed by using a 70 nm 3-metal CMOS process with a 1.35V supply. The current consumption and phase correction range were 2.73mA and +/- 8%, respectively.
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Collections - School of Electronic Engineering > 1. Journal Articles
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