Gate Architecture Effects on the Gate Leakage Characteristics of GaN Wrap-gate Nanowire Transistors
- Authors
- Mallem, Siva Pratap Reddy; Im, Ki-Sik; Thingujam, Terirama; Lee, Jung-Hee; Caulmilone, Raphael; Cristoloveanu, Sorin
- Issue Date
- Sep-2020
- Publisher
- KOREAN INST METALS MATERIALS
- Keywords
- GaNOI; Nanowire; Wrap-gate transistor; Triangular; trapezoidal architectures; Corner angle
- Citation
- ELECTRONIC MATERIALS LETTERS, v.16, no.5, pp 433 - 440
- Pages
- 8
- Journal Title
- ELECTRONIC MATERIALS LETTERS
- Volume
- 16
- Number
- 5
- Start Page
- 433
- End Page
- 440
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/28339
- DOI
- 10.1007/s13391-020-00229-w
- ISSN
- 1738-8090
2093-6788
- Abstract
- Gate leakage current in lateral GaN wrap-gate nanowire transistors (WG-NWT) was investigated using current density-voltage (J(g)-V-g) characteristics at room temperature. We found that the gate leakage current is strongly dependent on the top corner angle of the gate architecture. This leakage current was characterized by considering hopping (Poole-Frenkel emission) and trap-assisted thermionic emission mechanisms. Despite its smaller gate area, the gate leakage current of the lateral GaN WG-NWT without a 2DEG channel was higher than that of the device with a 2DEG channel for all applied gate biases. The reason for this is that the lateral GaN WG-NWT without 2DEG channel has a triangular cross-section with a sharp top corner angle resulting in a strong electric field due to geometrical field enhancement.
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